1. Field of the Invention
The present invention relates to a data transfer apparatus and method, and more particularly to a data transfer apparatus having a DMA (Direct Memory Access) controller, and a method for the same.
2. Description of the Related Art
In small computers, DMA transfer is employed which transfers data directly between an I/O device and a memory or between memories without the intervention of the CPU, and a DMA controller is used for such DMA transfer. Loaded with a memory address, transfer size, and other values, the DMA controller is activated to execute a DMA transfer.
In recent years, a method for controlling the DMA controller through descriptor control has been proposed in order to prevent system efficiency degradation which can occur when the host system controls data transfers in real time (refer, for example, to Japanese Unexamined Patent Publication No. 5-204829).
FIG. 20 is a format diagram showing one example of a descriptor format according to the prior art. In the example shown here, one address information (AD) and one byte count information (BC) are paired to form one descriptor information.
The address information (AD) indicates the starting point (address) of the DMA transfer data stored in a storage mechanism, and consists of 32 bits (bits 31 to 00). The byte count information (BC) indicates the amount of the DMA transfer data, and consists of 32 bits (bits 31 to 00) of which bits 31 to 14 are reserved bits and bits 13 to 00 are the actual byte count bits.
FIG. 21 is a schematic diagram showing one example of the structure of a descriptor storage mechanism for storing the descriptor shown in FIG. 20. The descriptor storage mechanism shown here can hold a plurality of descriptors (in the illustrated example, five descriptors indicated by i=1, 2, . . . , 5) each comprising address information ADi and byte count information BCi.
FIG. 22 is a diagram for explaining how the DMA controller fetches descriptor information according to the prior art. The DMA controller and the descriptor storage mechanism are connected via a common bus, and the DMA controller reads, via the common bus, the address information and the byte count stored in the descriptor storage mechanism. The DMA controller executes a DMA transfer based on the thus readout address information and byte count.
FIG. 23 is a format diagram showing another example of the descriptor format according to the prior art. In the example shown here, one address information (AD), one byte count information (BC), and one next descriptor address (ND) together constitute one descriptor information.
The difference from the example shown in FIG. 20 is that, in FIG. 23, bit 31 in the byte count information (BC) is used as a chain bit (C). This chain bit is a bit that indicates whether a plurality of DMA transfers are to be executed in succession, that is, a descriptor chain is to be executed; when this bit is ON, the next descriptor address is carried in the next area. The next descriptor address indicates the storage location of the descriptor information to be read next.
FIG. 24 is a schematic diagram showing one example of the structure of a descriptor storage mechanism for storing the descriptor show in FIG. 23. As shown, the descriptor storage mechanism can hold a plurality of descriptors (in the illustrated example, five descriptors indicated by i=1, 2, . . . , 5) each comprising address information ADi, byte count information BCi, and a next descriptor address NDi.
FIG. 25 is a diagram for explaining how the DMA controller fetches the descriptor information stored in the descriptor storage mechanism of FIG. 24. As shown in FIG. 25, when a descriptor chain is supported, the DMA controller executes a DMA transfer by fetching the next descriptor address in addition to the address information and the byte count.
Here, when the descriptor information is stored in its entirety in the descriptor storage mechanism as described above, if the storage areas, etc. for DMA control are large in size or in number, the amount of information carried in the descriptor becomes large, necessitating a corresponding increase in the size of the storage mechanism for storing the descriptor information, and hence resulting in an increase in the amount of hardware.
Furthermore, when the amount of information carried in the descriptor becomes large, as the number of transfers of the descriptor information increases, the number of times the common bus is used increases, making the common bus unavailable for other processing operations; this can result in a degradation of system performance.
On top of that, if a descriptor chain is to be executed, as the next descriptor address becomes necessary, the amount of information carried in the descriptor further increases, requiring an increase in the size of the storage mechanism for storing the descriptor information, and as a result, the amount of hardware further increases.
Furthermore, when the next descriptor address is added, the number of transfers of the descriptor information increases, increasing the number of times the common bus is used and thus making the common bus unavailable for other processing operations; this can result in a further degradation of system performance.